Phase-locked loops (PLLs) are used in data communications and telecommunications applications to lock onto the frequency of a signal. In particular, PLLs are often used in serializer/deserializer (SerDes) applications. A typical PLL includes a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO) that produces a VCO signal. A central component in ensuring signal lock is the phase detector. There are generally two classes of phase detectors, analog and digital. With a digital phase detector, if the frequency difference between the input and VCO signals is too large (typically greater than 1%), it is difficult for the PLL to achieve lock. Separate frequency detectors have been added to PLLs with digital phase detectors to ensure that the PLLs are able to achieve lock when the frequencies of the input and VCO signals are far apart (i.e., outside the capture range of the digital phase detector). The frequency detector of a PLL provides a frequency measurement of the VCO signal that is used to determine whether or not the frequency detector should assert control over the VCO signal. If the frequency detector is to assert control over the VCO signal, then the frequency detector is used to pull the frequency of the VCO signal close to a pre-established target frequency. Once the frequency of the VCO signal is within the capture range of the phase detector, control of the VCO is switched over to the phase detector.
One type of frequency detector, which is disclosed in U.S. patent application Ser. No. 10/714,037, filed Nov. 14, 2003, and entitled PROGRAMMABLE FREQUENCY DETECTOR FOR USE WITH A PHASE-LOCKED LOOP, utilizes a counter that counts the transitions of the VCO signal over a known sampling period to measure the frequency of the VCO signal. The timing of the transition sampling is tied to an external reference clock that is not synchronized with the VCO signal. Because the reference clock signal and the VCO signal are not synchronized, it is possible that the rising edges of the VCO signal and the signal that enables the counter could coincide with each other and cause the counter to be driven into a temporary metastable state. The metastable state of the counter can cause the counter to have an inaccurate value at the end of the respective sampling period. If the metastable state causes the counter value to be higher or lower than it should have been at the end of the sampling period, then the inaccurate counter value could cause the frequency detector to assert control over the VCO signal even though the frequency of the VCO is within the established deadband region. Although metastable-induced errors would likely be rare, they are unacceptable in some applications.
One technique for controlling metastable-induced errors involves passing the counter enable signal through a series of flip-flops, which are driven by the VCO, before the enable signal is applied to the counter. Passing the counter enable signal through a series of flip-flops gives time for a metastable state to resolve itself before reaching the counter and ensures that the rising edges of the VCO and retimed enable signals do not coincide. A drawback to passing the counter enable signal through a series of flip-flops is that the performance requirements of the flip-flops dictate the use of high power flip-flops, such as common mode logic (CML) flip-flops. In addition to consuming relatively large amounts of power, high power flip-flops typically require a large area on an integrated circuit (IC) chip compared to full-swing library cell flip-flops. Additionally, buffer amplifiers are required because all of the flip-flops must be driven by the same VCO signal.
In view of the above, what is needed is a technique for operating a PLL that reduces the likelihood that the frequency detector will incorrectly assert control over the VCO because of metastable-induced errors.